Example embodiments of present invention relate to a bus system and a method of arbitrating the same. For example, example embodiments of the present invention may relate to an Advanced High-performance Bus (AHB) system having a plurality of masters, that is capable of reducing or preventing system failure when an early termination occurs in a burst mode.
In complicated computer systems, a plurality of processors and various peripheral devices may be used for exchanging data between integrated chips (ICs) or between the ICs and an external device. Some computer systems use various, separate buses for transferring data. Such multiple bus systems require bus controller(s) for collision-free communication between the separate buses. For such a purpose, a microcontroller has been used. The microcontroller may provide a bus arbitration function to decide which device has control of a bus at a given time.
A standard AMBA interface may include two main buses, i.e., an advanced high-performance bus (AHB) and an advanced peripheral bus (APB). The AHB may be a main memory bus, which may be connected to a random access memory (RAM) and an external memory controller.
FIG. 1 is a block diagram illustrating a prior art AHB system including a master, a slave and an arbiter.
Referring to FIG. 1, in the AHB system, signals flow back and forth among at least are AHB master which requests control of an AHB 100, an AHB arbiter 110 which executes arbitration decisions, and at least one AHB slave 210 which is selected by the master. The AHB arbiter 110, the AHB master 200 and the AHB slave 210 may receive a reset signal (HRESET) 222, and/or a clock signal (HCLOCK) 223. The AHB master 200 may activate a bus control request signal (HBUSREQX) 231 so as to request a control of the AHB 100 from the AHB arbiter 110, and may receive a bus access grant signal (HGRANTX) 232 from the AHB arbiter 110 to be granted access to the AHB 100. After the grant, the AHB master 200 may lock an arbitration decision according to a clock signal HLOCKX 233, and may send an address signal (ADDRESS) 205 to an AHB decoder 111. The AHB decoder 111 may activate a selection signal 112 to be provided to the AHB slave 210.
Mutual interactions between the AHB master 200 and the AHB slave 210 may be carried out by control signals (CONTROL) 213, and may be acknowledged by a response signal HRESP 211 and a ready signal HREADY 212. Data for a read operation or for a write operation may be transferred from the at least one AHB master 200 via the AHB 100 to the at least AHB slave 210. The AHB slave(s) 210 may provide data to the AHB 100 through an HRDATA bus 206, and may receive data from the AHB 100 through an HWDATA bus 207. Similarly, the AHB master(s) 200 may provide data to the AHB 100 through an HWDATA bus 209, and receive data from the AHB 100 through an HRDATA bus 208. At any given time, one AHB master 200 may be activated. The activated AHB master 200 may select only one AHB slave 210 to execute the read operation or the write operation.
According to the AMBA Specification Rev. 2.0, a memory controller that supports early termination is required to monitor addresses and control signals, for each cycle, in a burst mode. A memory controller with early termination support may be more complex and/or more unreliable, when operated at a higher speed than memory controllers without early termination support.
Therefore, memory controllers, which may be slave devices, tend not to support early termination for improving speed. In addition, in most systems-on-chips (SOCs), support of early termination is excluded from master devices, for example, a direct memory access (DMA) controller, a liquid crystal display (LCD) controller, and the like, except for ARM9 processors.
In a system including an ARM9 processor from ARM, Ltd., master devices, for example, a DMA, etc. and slave devices, for example, a memory controller, the master devices may have different priorities related to usage of the AHB. In such cases, the AHB arbiter may arbitrate access to the AHB between the master devices according to the priorities. Thus, whenever accessing the AHB slave devices, e.g., the memory controller, the master devices may send a request signal for controlling the AHB to the AHB arbiter and receive a grant signal for controlling the AHB, so as to access the memory controller via the AHB.
When the ARM processor, after receiving the grant signal, executes a burst mode operation, the AHB arbiter may be requested from a master device having a priority higher than that of the ARM processor. The AHB arbiter may revoke the grant signal previously granted to the ARM processor, and give the grant to the master device having a higher priority. The control of the AHB may possibly be handed over to the master device having a higher priority even before the ARM processor in the burst mode operation can finish reading or writing data. Such an incident is referred to as an early termination. A memory controller, without early termination support, may fetch data from an external memory, for example, a dynamic random access memory (DRAM), according to the number of the bursts in the first cycle of the burst mode operation, and may transfer the fetched data not to the ARM processor, but to the master device having a higher priority in the second cycle of the burst mode operation without taking into account the fact that the control of the AHB has been handed over. As a result, the early termination may cause a failure of data transfer.